Pin Configuration
IN
SD
DT
V DD
LO1
LO2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V B
HO1
HO2
V S
NC
NC
NC
FAN7383 Rev:00
Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Name
IN
SD
DT
V DD
LO1
LO2
GND
N.C.
N.C.
N.C.
V S
HO2
HO1
V B
Description
Logic Input for Gate Driver
Logic Input for Shutdown (Active Low)
Programmable Dead-Time Control with External Resistor
Low-Side Supply Voltage
Low-Side Driver Source Output
Low-Side Driver Sink Output
Ground
Not connected
Not connected
Not connected
High-Side Floating Supply Return
High-Side Driver Sink Output
High-Side Driver Source Output
High-Side Floating Supply
? 2006 Fairchild Semiconductor Corporation
FAN7383 Rev. 1.0.3
4
www.fairchildsemi.com
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